1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly, to pseudo Static Random Access Memory (SRAM) and operation control methods thereof.
2. Discussion of Related Art
Semiconductor memory devices include SRAM and a Dynamic Random Access Memory (DRAM). SRAM is advantageous in that it does not need a refresh operation for data retention since it has memory cells of a latch structure and has a fast operation speed and low power consumption in comparison with DRAM. SRAM is, however, disadvantageous in that it is larger in size than DRAM and is expensive, due to the area occupied by the memory cells of the latch structure.
Meanwhile, DRAM includes memory cells, each having one transistor and one capacitor. Since a leakage current is generated in the memory cells constructed above, data stored in DRAM memory cells is lost due to the leakage current as times goes by. Therefore, DRAM is disadvantageous in that it must perform a refresh operation periodically in order to retain data. Furthermore, DRAM has an operating speed slower than that of SRAM and has high power consumption than SRAM. However, since DRAM includes memory cells having an occupation area smaller than that of SRAM, it is advantageous in terms of integration level and price in comparison with SRAM.
Recently, as the level of integration of semiconductor memory devices becomes higher and there is a need for a higher speed, semiconductor memory devices of a high performance, which have only advantages of SRAM and DRAM, such as pseudo SRAM, have been developed by implementing SRAM using DRAM cells. Pseudo SRAM is a semiconductor memory device including memory cells having DRAM cell structure and peripheral circuits of SRAM. In pseudo SRAM, an additional SRAM cache memory continuously performs the read and write operations of data even when DRAM cells perform the refresh operation. Therefore, pseudo SRAM operates in a similar way as SRAM by hiding the refresh operation of the DRAM cells externally.
Pseudo SRAM in the related art, however, does not support a burst mode of reading or writing data in burst in response to one access command. Therefore, pseudo SRAM in the related art can perform read or write operation of data on only memory cells connected to one word line in response to one access command. As a result, a problem arises because the related art pseudo SRAM has to receive corresponding new external address signals whenever word lines that should be enabled in order to perform the read or write operation are changed.